PLL(Phase-locked loop)

PLL, 鎖相迴路
以下截至wiki之重點：

锁相环（PLL: Phase-locked loops）是一种利用反馈（Feedback）控制原理实现的频率及相位的同步技术，其作用是将电路输出的时钟与其外部的参考时钟保持同步。当参考时钟的频率或相位发生改变时，锁相环会检测到这种变化，并且通过其内部的反馈系统来调节输出频率，直到两者重新同步，这种同步又称为“锁相”（Phase-locked）。

"PLL" redirects here. For other uses, see PLL (disambiguation).

A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and aphase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called afeedback loop since the output is 'fed back' toward the input forming a loop.

Refer to : http://en.wikipedia.org/wiki/Phase-locked_loop